The present invention relates to the fabrication of semiconductor devices, particularly to self-aligned silicide (salicide) technology, and the resulting semiconductor devices. The present invention is particularly applicable to ultra large scale integrated circuit (ULSI) systems having features in the deep sub-micron size range.
As integrated circuit geometries continue to plunge into the deep sub-micron regime, it becomes increasingly more difficult to accurately form discreet devices on a semiconductor substrate exhibiting the requisite reliability. High performance microprocessor applications require rapid speed of semiconductor circuitry. However, scaling down device components such as source and drain junctions, and scaling down the width of polycrystalline silicon lines, increases parasitic resistance in the source and drain disunion layers and gate electrode diffusion layer, and also increases the sheet and contact resistance of the gate electrode and source and drain regions. Since the speed of semiconductor circuitry is adversely affected by high resistance, low resistivity interconnection paths are critical to fabricating dense, high performance devices.
A common approach to reduce the resistivity of the interconnects to less than that exhibited by polysilicon alone, e.g., less than about 15-300 ohm/sq, comprises forming a multilayer structure consisting of a low resistance material, e.g., a refractory metal silicide, on a doped polycrystalline silicon layer, typically referred to as a polycide. Advantageously, the polycide gate/interconnect structure preserves the known work function of polycrystalline silicon and the highly reliable polycrystalline silicon/silicon oxide interface, since polycrystalline silicon is directly on the gate oxide.
Various refractory metal suicides have been employed in polycide technology, such as titanium, tungsten, and cobalt silicides. Nickel, however, offers particular advantages vis-à-vis other metals. Nickel requires a lower thermal budget; that is, nickel silicide and can be formed in a single heating step at a relatively low temperature of about 250xc2x0 C. to about 600xc2x0 C. with an attendant reduction in consumption of silicon in the substrate, thereby enabling the formation of ultra-shallow source/drain junctions.
In conventional self-aligned silicide, or xe2x80x9csalicidexe2x80x9d technology, a layer of the refractory metal is deposited on a gate electrode, typically comprising polysilicon with dielectric sidewall spacers, and on exposed surfaces of the source/drain regions, followed by heating to react the metal with underlying silicon to form the metal silicide. Unreacted metal is then removed from the dielectric sidewall spacers leaving metal silicide contacts on the upper surface of the gate electrode and on the source/drain regions. In implementing salicide technology, it is also advantageous to employ silicon nitride sidewall spacers, since silicon nitride is highly conformal and enhances device performance, particularly for p-type transistors. However, although silicon nitride spacers are advantageous from such processing standpoints, it is extremely difficult to effect nickel silicidation of the gate electrode and source/drain regions without undesirable nickel silicide bridging and, hence, short circuiting, therebetween along the surface of the silicon nitride sidewall spacers.
Accordingly, there exists a need for salicide methodology enabling the implementation of nickel silicide interconnection systems without bridging between the nickel silicide layers on the gate electrode and the source/drain regions, particularly when employing silicon nitride sidewall spacers on the gate electrode.
An advantage of the present invention is a method of manufacturing a semiconductor device having nickel silicide contacts on a gate electrode and associated source/drain regions without bridging therebetween along insulative sidewall spacers, notably silicon nitride sidewall spacers.
Additional advantages and other features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned by practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising forming a gate electrode, having opposing side surfaces, on a substrate with a gate insulating layer therebetween; forming silicon nitride sidewall spacers on the opposing side surfaces of the gate electrode, leaving exposed adjacent surfaces of the substrate; implanting exposed surfaces of the silicon nitride sidewall spacers with nitrogen; depositing a layer of refractory metal on the gate electrode and the exposed surfaces of the substrate; and heating to react the metal layer with underlying silicon to form a layer of metal silicide on the gate electrode and a layer of metal silicide on the exposed surfaces of the substrate.